1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device.
2. Background Art
IGBTs (insulated gate bipolar transistors) having trench gate structures are conventionally used as power devices for EVs (electric vehicles), EHVs (electric and hybrid vehicles), and the like, for example. The trench gate structure has a gate electrode embedded in a trench through an oxide film, and the trench is formed in the surface of the semiconductor substrate. The trench gate structure can be modified to have a finer cell structure than a coplanar gate structure having a gate electrode on the surface of the semiconductor substrate. A method of manufacturing a vertical IGBT having a trench gate structure will be explained below.
FIGS. 18 to 20 are cross-sectional views of a conventional semiconductor device during manufacturing. As shown in FIG. 18, a p-type base region 102 is first formed in the front surface layer of an n− semiconductor substrate (silicon (Si) substrate), which will serve as an n− drift layer 101. Next, a trench 103 that reaches from the substrate front surface to the n drift layer 101 by going through the p-type base region 102 is formed. Next, a thermal oxidation treatment and poly-Si doping are performed in the stated order, and etch-back is used to form a gate electrode 105 in the trench 103 through a gate insulating film (gate oxide film) 104. A thin oxide film (not shown), which will serve as a buffer layer for ion implantation, is then formed on the front surface of the n− semiconductor substrate. The ion implantation will be explained later.
Next, photolithography is performed to form a resist mask 111 on the front surface of the n− semiconductor substrate, and the open portions of this resist mask correspond to the area where a p+ contact region 106 will be formed. Ion implantation 112 is then performed with this resist mask 111 to inject boron (B) at an implantation angle that is perpendicular to the front surface (primary surface) of the substrate. This selectively forms the p+ contact region 106 in the surface layer of the p-type base region 102 near the center of an area (hereinafter, “mesa area”) sandwiched by adjacent trenches 103. Next, the resist mask 111 is removed. As shown in FIG. 19, photolithography is then performed to form a resist mask 113 on the front surface of the n− semiconductor substrate, and the open portions of this resist mask correspond to the gate electrode 105 and the area where an n+ emitter region 107 will be formed.
Next, ion implantation 114 is performed with this resist mask 113 and the gate electrode 105 as masks to inject arsenic (As) at an implantation angle that is perpendicular to the front surface of the substrate. This selectively forms the n+ emitter region 107 on the front surface layer of a portion of the p-type base region 102 (mesa area) sandwiched by the trench 103 and the p+ contact region 106. The n+ emitter region 107 is formed to contact a portion of the gate insulating film 104 extending along the sidewall of the trench 103. The resist mask 113 is then removed. Next, as shown in FIG. 20, activation and thermal diffusion are performed by heat treatment, and the p+ contact region 106 and n+ emitter region 107 are set to respectively prescribed diffusion depths. The n+ emitter region 107, in particular, is thermally diffused such that the top of the gate electrode 105 is positioned at a height inside the n+ emitter region 107. Thereafter, conventional methods are used to form an interlayer insulating film, emitter electrode, p+ collector layer, collector electrode (none shown in drawing), and the like, thereby completing the trench gate structure IGBT.
The following device has been proposed as a different trench gate structure MOS (metal-oxide film-semiconductor) semiconductor device. Among the first and second source regions and source contact regions, the first source region is closest to the gate electrode around the trench, and the second source region and source contact region are separated in this order from the gate electrode. The depth of the first source region is less than the depth of the second source region. The first source region is formed shallower by shortening the diffusion time, lowering the diffusion temperature, or adjusting the impurity implantation dosage (see Patent Document 1 below (paragraph [0018]), for example).
A different method of manufacturing the trench gate structure MOS (metal-oxide film-semiconductor) semiconductor device has been proposed as follows. Arsenic is selectively implanted in the p-type well region. During this time, arsenic is implanted perpendicular to the substrate surface from two directions: a slanted direction that tilts toward one lengthwise direction of the trenches, and a slanted direction that tilts towards the other direction. The implantation angle is 10 to 30 degrees perpendicular to the substrate surface. Next, heat treatment is performed to diffuse and activate the arsenic, thereby selectively forming an n+ source region in the surface layer of the p-type well region. Thereafter, a p+ well contact region is formed in the surface layer of an area of the p-type well region sandwiched by the n+ source regions (see Patent Document 2 below (paragraphs [0030] to [0033], FIG. 6), for example).
Furthermore, a method has been proposed, as another method of manufacturing a trench gate structure MOS semiconductor device, whereby differing ion implantations are used to form a p-type contact region, n-type source region, and p-type counter region (p-type contact region) in the stated order. After this, these regions are collectively heat treated to diffuse and active the impurities (see Patent Document 3 below (paragraphs [0154] to [0155], FIG. 17, for example).
In Patent Document 3, ion implantation of arsenic is performed with the resist mask and the gate electrode in the trench as masks in order to form the n-type source region. Performing ion implantation in this manner to form the n-type source region on the surface of the gate electrode (trench top) without a resist mask prevents the n-type source region from being formed separate from the gate insulating film on the trench sidewall.